1. Field
Aspects of the present disclosure relate generally to frequency synthesis, and more particularly, to phase locked loops (PLLs).
2. Background
A phased locked loop (PLL) may be used in frequency synthesis to generate a signal having a desired frequency by multiplying the frequency of a reference signal by a corresponding amount. PLLs are widely used to provide signals having desired frequencies in wireless communication systems, micro-processing systems, and high-speed data systems.